Volume 2 Number 3 (May 2012)
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IJAPM 2012 Vol.2(3): 149-151 ISSN:2010-362X
DOI: 10.7763/IJAPM.2012.V2.73

TCAD Simulation of Digital Logic Gates in Independent Double Gate Transistors – A Comparative Study between Conventional and Junctionless FETs

Bhima Harsha, K. K. Nagarajan, and R. Srinivasan

Abstract—In this work, conventional independent double gate structure and Junctionless independent double gate structure-based inverters and NAND gates are studied and compared using TCAD simulation. The Junctionless device-based circuits show a larger delay with smaller dynamic power whereas the conventional device-based circuits show smaller delay with larger dynamic power which is a simple power-delay trade-off.

Index Terms—Junctionless FET, FinFET, NAND, inverter, TCAD.

B. Harsha and R. Srinivasan are with IT Department, SSN college of Engineering, Kalavakkam, Chennai (email: bhima.harsha@gmail.com).
K. K. Nagarajan is with MCA Department, SSN college of Engineering, Kalavakkam, Chennai.

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Cite: Bhima Harsha, K. K. Nagarajan, and R. Srinivasan, "TCAD Simulation of Digital Logic Gates in Independent Double Gate Transistors – A Comparative Study between Conventional and Junctionless FETs," International Journal of Applied Physics and Mathematics  vol. 2, no. 3, pp. 149-151, 2012.

General Information

ISSN: 2010-362X
Frequency: Bimonthly (2011-2014); Quarterly (Since 2015)
DOI: 10.17706/IJAPM
Editor-in-Chief: Prof. Haydar Akca
Abstracting/ Indexing: Index Copernicus, EI (INSPEC, IET), Chemical Abstracts Services (CAS), Electronic Journals Library, Nanowerk Database, Google Scholar, EBSCO, and ProQuest
E-mail: ijapm@iap.org
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